FinFET and FDSOI Solutions for ESD and Analog I/Os

CEO Koen Verhaege talks about ESD protection solutions for advanced FinFET (16nm to 5nm) and SOI technologies (22nm). For each case the challenges, solutions and supporting data are discussed.

Application specific challenges include
(1) Requirement for low-cap ESD solution for high-speed or high bandwidth interfaces
(2) Requirement for high voltage tolerance for communication with legacy chips
(3) Requirement for low leakage ESD protection for battery powered applications

Technology related challenges include
(1) closing ESD design window in advanced processes
(2) more resistive connections on lower metal connections
(3) non-effective conventional ESD devices

Solutions include full local interface protection. Sofics IP provides ESD clamps with small footprint, low on-resistance, low capacitance, low leakage

Koen introduces FinFET and FDSOI data to demonstrate robustness, benchmarked against the PDK devices. He also provides an assessment for CDM protection.

Contact Sofics or read more on our website.

Тэги:

#On-chip_ESD_protection #ESD_protection #Electrostatic_Discharge #ESD #TSMC #Sofics #IC_design #Semiconductor #Chip_design #FinFET #N16 #N12 #N7 #N5 #16nm #12nm #7nm #5nm #IC_design_complexity #EUV #Nanometer_IC_design #Increase_IC_robustness #Improve_IC_performance #Reduce_IC_cost #Reliability #Silicon_proven #Fabless_IC_design #FF #FDSOI #analog_I/Os

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