SOFICS SHORT FF-FDSOI ESD Design Window

With declining feature sizes, the intrinsic ESD sensitivity of circuit nodes increases. In this short movie, we introduce the concept of the ESD design window – which is becoming narrower as technology advances. Standard PDK solutions introduce circuit design restriction to cope with the challenge. We introduce Sofics solutions that fit the narrow design windows. This opens opportunities to use core gates in I/Os and relax the ESD design constraints.

Тэги:

#On-chip_ESD_protection #ESD_protection #Electrostatic_Discharge #ESD #TSMC #Sofics #IC_design #Semiconductor #Chip_design #FinFET #N16 #N12 #N7 #N5 #16nm #12nm #7nm #5nm #IC_design_complexity #EUV #Nanometer_IC_design #Increase_IC_robustness #Improve_IC_performance #Reduce_IC_cost #Reliability #Silicon_proven #Fabless_IC_design #FDSOI #ESD_Design_Window

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